VLSI Design

VLSI Design

VLSI Design in EDWinXP

The VLSI design in EDWinXP is made possible by the VHDL Editor present in the software. This helps to input VHDL codes with syntax of Level 0 type.

VHDL Editor

VHDL Editor is basically an editor for writing VHDL source files. Its working is very much similar to any normal programming editor. All keywords present in the source are highlighted in blue. The source code may be compiled and error messages displayed to help quick debugging

Invoking VHDL Editor

This module may be invoked from Project Explorer in the following ways.

Right click System and select VHDL Editor from the list.

Select VHDL Editor from the Tasklist or from the Task toolbar.

Note: By default, the task toolbar will not be displayed. It may be enabled from View menu in the Project Explorer.

The VHDL Editor opens as shown below:

Some main features of VHDL Editor are:

1. It compiles the source file and generates wirelist (*.wrs) output file.
2. The output file (*.wrs) may be imported directly to the system.
3. It helps to generate simulateable models in Mixed Mode & EDSpice Model Generators.
4. Helps to convert the (*.wrs) file to Xilinx, CUPL and JEDEC formats.

The code can be written in the workspace and can be compiled from Build --> Compile (F7).

The circuit can be used to import EDWinXP by Build --> Compile and Import.

Convert VHDL Code to diagram

This function enables conversion of VHDL code into schematic diagram.

Conversion procedure is divided into three steps using dialog invoked from menu Tools - > Convert VHDL Code to diagram.

Step1-Specifying the number of Inputs/Outputs & Processing options

In the dialog that opens, the maximum number of inputs/outputs is limited to eight. Inputs and outputs have settable name prefixes and are numbered from 0 to 7.

The VHDL code is converted to schematic diagram, which may be included in the project in three ways:

Diagram may be appended to currently edited page.
Diagram may be appended as a new page in currently selected circuit.
Diagram of a new circuit may be added to the project.

Components in the diagrams resulting from conversion of VHDL code may be automatically placed according to selected placement in the schematic. The nodes connecting wires are automatically routed. These automatic functions are optional. Diagrams where auto placement option is deactivated cannot be auto routed.

Step2-Editing the code in VHDL Editor

Clicking ‘Next’ button opens VHDL Editor. VHDL Entity Template is automatically generated.

After writing the required code (in any level of abstraction), save and compile.

Step3-Finishing Conversion

The successful compilation of VHDL code will result in the VHDL code conversion to schematic wire list format. The file with wire list is stored in temporary folder under fixed name ‘True TableNetlist.wrs’. Listing of this file may be invoked from the dialog that pops up when conversion is successfully completed. This dialog allows setting finishing options for processing of diagram - like page format and parameters for automatic topological placement of components.

After clicking ‘Finish’ button, the netlist is imported, components placed and all the connections are routed. The new diagram may be placed in desired position on the page.